Estimation of the Signal - to - Noise Ratio for On - Chip Wireless Clock Signal Distribution ( Year 2000 ) ' Daniel

The achievable signal-to-noise ratio for an 18-GHz wireless clock distribution system has been estimated by extrapolating from the current status of the clock receiver, the integrated antenna performance, and the understanding of noise sources and coupling mechanisms. It is estimated that a SNR of -23 dB is achievable at the input of the frequency divider within the clock receiver block. Introduction With the increase of both operating frequencies and die sizes, the global clock distribution has become one of the major problems in designing high performance microprocessors. A potential alternative solution is the use of a wireless clock distribution system where a high frequency clock signal is transmitted at the speed of light using microwaves [I]. The wireless clock distribution system consists of a transmitter, located on or off chip, broadcasting a microwave global clock signal at frequencies of -20-GHz or higher, and a grid of integrated clock receivers (Fig. l(a)). The signal picked up by the receiving antenna is divided down to provide the system clock frequency (-2.5-GHz) (Fig. l(b)), and locally distributed using a conventional clock tree. In order to make a wireless clock distribution system work, a sufficiently high signal to noise ratio (SNR) must be provided at the input to each receiver block. A low SNR will translate into problems such as clock skew, missed clock cycles, and ultimately the loss of the entire clock signal. The required SNR to avoid or to adequately reduce these problems is being evaluated. To complement this, the best SNR which can be presently achieved has been estimated, and the results and methodology used for the estimation are presented in this paper. The SNR is estimated by extrapolating from the current status of the clock receiver, the integrated antenna performance, and the current understanding of noise sources and coupling mechanisms. The resulting number is certain to change with time as the clock receiver and antenna performances are improved, and the understanding of noise sources and coupling is increased. For this reason, the results presented here should be treated as approximate figures which can be used for evaluating the first order feasibility of such a system when the required SNR for wireless clock distribution becomes available, and more importantly, to iden' This work is supported by Semiconductor Research Corporation Cont. 96-U-453. tify the problem areas so that the clock distribution system can be improved. Signal-to-Noise Estimation There are numerous factors that must be considered when estimating the maximum achievable SNR for an on-chip wireless clock distribution system. These factors include signal transmission power, integrated antenna power transmission gain, interference effects of chip packaging and on-chip metal lines, thermal noise, and noise coupled to the antennas by on-chip digital circuitry. For the purposes of this paper, a signal transmission power of +10 dBm has been chosen. This is within the comfortable range of achievable signal power for an on-chip transmitting circuit block. Each clock receiver block consists of a low-noise amplifier (LNA) which feeds a frequency divider circuit (Fig. l(b)). The LNA has a tuned response centered around the frequency of the transmitted global clock signal. The current target for the global clock signal is between I8 and 20-GH2, however due to the present limited access to process technologies capable of supporting such frequencies (0.13-pm CMOS generation and beyond), the noise and clock receiver characteristics are extrapolated from the circuits fabricated in a 0.25-pm CMOS test chip. The LNA on this receiver has a tuned frequency of -8-GHz (Fig. 2), while the digital circuits used for the investigation of. noise coupling operate at -2-